View HIP0050_138012.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HIP0050
December 1996
0.3A/50V Octal Low Side Power Driver with Serial Bus Control and Over-Current Fault Flag
Description
The HIP0050 is a logic controlled, eight channel Octal Low Side Power Driver. As shown in the block diagram, the outputs are controlled via the serial data interface which allows the data to be shifted out, allowing control of other cascaded serial devices. If an Over-Current (OC) short circuit exists in one output, it may be independently shutdown while the other outputs remain in operation. When a shorted output is latched off, it may be turned back on when the next serial input data is latched. A fault flag (FLT) is set to a low status to indicate current-limited shutdown. The outputs are independently latched off when an OC fault is detected. The fault latch is cleared on the next data strobe. Over-Temperature (OT) shutdown is provided with hysteresis to force global shutdown of all output drivers. Shutdown is maintained until the on-chip temperature falls below the minimum hysteresis threshold point. The HIP0050 is fabricated in a Power BiMOS IC process, and is intended for use in automotive and other applications having a wide range of temperature and electrical stress conditions. It is particularly suited for driving lamps, displays, relays, and solenoids in applications where low operating power, high breakdown voltage, and high output current at high temperature is required. Higher current needs can be met by paralleling adjacent output drivers.
Features
* Octal NDMOS Output Drivers in a High Voltage Power BiMOS Process - Each Capable of Sinking 300mA - Low Idle and Standby Current * Over-Stress Protection - Each Output: - Over-Current Latch Off . . . . . . . . . 300mA Min - Over-Voltage Clamp . . . . . . . . . . . . . . . 50V Typ * Thermal Shutdown with Hysteresis * Serial Data Input, Parallel Output Power Drive * Short Circuit Latch Off for Each Output * Common Enable for Output Drivers and Data Storage Register * Ambient Operating Temperature Range. . . . . . . . . . . . .-40oC to 85oC - Optional 125oC Maximum Ambient Operating Temperature Range (Dissipation Limited)
Applications
* Automotive and Industrial Systems * Solenoids, Relays and Lamp Drivers * Logic and P Controlled Drivers * Robotic Controls
Ordering Information
PART NUMBER HIP050IP HIP0050IB TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 20 Ld PDIP 24 Ld SOIC PKG. NO. E20.3 M24.3
Pinouts
HIP0050 (PDIP) TOP VIEW
DR2 DR3 FLT EN GND GND STR SCK DR4 1 2 3 4 5 6 7 8 9 20 DR1 19 DR0 18 SI 17 VCC 16 GND 15 GND 14 LGND 13 SO 12 DR7 11 DR6 DR2 1 DR3 2 FLT 3 EN 4 GND 5 GND 6 GND 7 GND 8 STR 9 SCK 10 DR4 11 DR5 12
HIP0050 (SOIC) TOP VIEW
24 DR1 23 DR0 22 SI 21 VCC 20 GND 19 GND 18 GND 17 GND 16 LGND 15 SO 14 DR7 13 DR6
DR5 10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
4034.1
1
HIP0050 Block Diagram
OUTPUT DRIVER (ENABLE) EN (STROBE) STR Q0 SI SERIAL (SPI) INPUT REGISTER (DATA IS PARALLEL OUTPUT LATCHED WHEN STROBED) Q1 Q2 POR Q3 Q4 Q5 Q6 Q7 OVER-TEMPERATURE SHUTDOWN W/HYS FLT S R FAULT LATCH OC SHUTDOWN (CHANNEL 1 OF 8) DR#0
OUTPUT LATCH
SCK
SO
Output Control Logic Table
STROBE D1 0 1 1 1 1 0 1 D2 0 0 1 1 1 0 1 8-BIT SERIAL DATA (LATCHED) D3 0 0 0 1 1 0 1 D4 0 0 0 0 1 0 1 D5 0 0 0 0 0 1 1 D6 0 0 0 0 0 1 1 D7 0 0 0 0 0 1 1 D8 0 0 0 0 0 1 1 DR1 OFF ON ON ON ON OFF ON DR2 OFF OFF ON ON ON OFF ON DR3 OFF OFF OFF ON ON OFF ON OUTPUT DR4 OFF OFF OFF OFF ON OFF ON DR5 OFF OFF OFF OFF OFF ON ON DR6 OFF OFF OFF OFF OFF ON ON DR7 OFF OFF OFF OFF OFF ON ON DR8 OFF OFF OFF OFF OFF ON ON
2
HIP0050
Absolute Maximum Ratings
Output Voltage, VOUT (Note 1) . . . . . . . . . . . . . . . . . . . -0.3V to VOC Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V Logic Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V Max Output Load Current, ILOAD (Per Output, Note 2) . . . . . . . . . ICL Max. Output Load Current, ILOAD (All Outputs ON, Note 2) . . . . . 2A Operating Ambient Temperature Range, TA . . . . . . . . -40oC to 85oC Operating Junction Temperature Range. . . . . . . . . . -40oC to 150oC Storage Temperature Range, TSTG . . . . . . . . . . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 10s Max). . . . . . . . . 300oC (Lead Tips Only)
Thermal Information
JC (oC/W) Package PDIP . . . . . . . . . . . . . SOIC . . . . . . . . . . . . . 10 10 JA (oC/W) 0 50 60 2 35 40

Versus Additional Square Inches 1oz. copper on PCB. Standard Test Board, 0.002 diameter T/C located at lead shoulder, middle lead.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Typical Logic Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . +5V ICC Supply Current, with 200mA each Output . . . . . . . . . . . . 2mA ICC Supply Current, with No Load . . . . . . . . . . . . . . . . . . . . . 2mA Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0V Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5V Power Output Driver Voltage Range . . . . . . . . . . . . . . . . . 0 to VOC Power Output Driver Current Load, IDR . . . . . . . . . . . . . . . . 0 to ICL Typical Output rDSON Channel Resistance . . . . . . . . . . . . . . . . 2 Typical Output Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4s Typical Output Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10s
Electrical Specifications
PARAMETER
VCC = 4.5V to 5.5V, VBATT = 8V to 16V, TA = -40oC to 85oC; Unless Otherwise Specified SYMBOL CONDITIONS MIN TYP MAX UNITS
OUTPUTS DRIVERS (DR0 TO DR7) Output Channel Resistance Output Over-Current Shutdown Threshold Output Clamping Voltage Output Clamping Energy Output OFF Leakage Current Output Rise Time Output Fall Time Output Delay from Strobe, High to Low Output Transition Output Delay from Strobe, Low to High Output Transition LOGIC SUPPLY Logic Supply Current, Loaded Logic Supply Current, No Load Logic Supply Under-Voltage Reset Threshold LOGIC INPUTS (EN, SI, SCK, STR) Threshold Voltage at Falling Edge Threshold Voltage at Rising Edge Hysteresis Voltage Leakage Current VT VT + VH VCC = 5V 10% VCC = 5V 10% V T + - VT 0.2VCC 0.85 -10 0.3VCC 0.6VCC 1.4 0.7VCC 2.25 10 V V V A ICC ICC All Outputs ON, 0.2A Load Per Output All Outputs OFF All Outputs OFF 3.5 2 2 4 4 4 mA mA V rDSON ICL VOC EOC IOFF tRISE tFALL tDHL tDLH Outputs OFF 1ms Single Pulse Width, TA = 25oC, (Refer to Figure 2 for SOA). Output Voltage = 40V, TA = 85oC Load = 75, 0.01F (Parallel) Load = 75, 0.01F (Parallel) Output Current = 200mA, TA = 85oC 300 42 0.5 0.5 1 0.2 2 50 25 4 10 4 2.6 4.0 500 58 10 30 30 10 10 mA V mJ A s s s s
I LIN
SERIAL DATA CLOCK (SCK) (Refer to Figure 1 for Waveform Detail) Frequency Pulse Width High fSCK tW(SCKH) 27 1.6 175 MHz ns
3
HIP0050
Electrical Specifications
PARAMETER Pulse Width Low VCC = 4.5V to 5.5V, VBATT = 8V to 16V, TA = -40oC to 85oC; Unless Otherwise Specified (Continued) SYMBOL t W(SCKL) CONDITIONS MIN TYP 27 MAX 175 UNITS ns
SERIAL DATA IN (SI) (Refer to Figure 1 for Waveform Detail) Input Setup Time Input Hold Time STROBE (STR) Strobe Pulse Width Clock to Strobe Delay t W(S) t D(CS) 12 5 150 75 ns ns t SUI THI 1.1 1.5 75 75 ns ns
SERIAL DATA OUT (SO) (Refer to Figure 1 for Waveform Detail) Low Level Output Voltage High Level Output Voltage Propagation Delay PROTECTION PARAMETERS Fault Output (FLT) Low Over-Temp. (OT) Shutdown OT Shutdown Hysteresis NOTES: 1. The MOSFET Output Drain is internally clamped with a Drain-to-Gate Zener Diode that turns on the MOSFET; holding the drain at the output clamp voltage VOC. 2. The HIP0050 Output Drive is protected by an internal current shutdown. The ICL over-current shutdown threshold parameter specification defines the maximum current. The minimum limit for this threshold is 300mA. The maximum current with all outputs ON may be further limited by dissipation. 3. Package dissipation is based on thermal resistance capability in a normal operating environment. The junction to ambient thermal resistance values are defined here as a PC Board mounted device with minimal copper. Due to the heat conducting capability of the DIP and SOIC package lead frames, 35oC/W thermal resistance can be achieved with approximately 2 square inches of 1 oz. copper PC Board area. The junction to lead thermal resistance values are based on measurements from the chip to the ground leads of the package. VOL TSD TH Sink Current = 1.6mA 145 5 155 10 0.4 165 20 V
oC o
VOL VOH t P(CD)
Sink Current = 1.6mA Source Current = -1.6mA
3.7 75
0.2 4.4 260
0.4 500
V V ns
C
t W(SCK) SCK (CLOCK) t SUI SI (SERIAL DATA IN)
t W(SCK)
t HI
t D(CS) STR (STROBE) t D(HL) t D(LH)
t W(S)
90%
DRx (POWER OUTPUT DRIVER) t P(CD) SO (SERIAL DATA OUT)
10%
t FALL, t RISE
FIGURE 1. LOGIC TIMING CONTROL WAVEFORMS
4
HIP0050 Pin Descriptions
VCC Power Pin The VCC pin is the positive 5V logic voltage supply input for the IC. The normal operating voltage range is 4.5V to 5.5V. When switched on, the POR forces all outputs off. SCK Serial Clock Pin SCK is the clock input for the SPI Interface. Output ON/OFF control data is clocked into an eight stage shift register on the rising edge of an external clock. This input has a Schmitt trigger. SI Serial Data In Pin SI is the Serial Data Input Pin for the SPI Interface. The eight power outputs are controlled by the serial data via the output data buffer. This input has a Schmitt Trigger. STR Strobe Pin for the SPI Interface When the STR Pin is high, data from the 8-bit shift register is passed into the output data buffers where it controls the ONOFF state of each output driver. The data is latched in the output data buffers when STR goes low. This input has a Schmitt trigger. SO Serial Data Out Pin The serial data out allows other ICs to be serially cascaded. For example, a 10-bit LED driver may be located behind the HIP0050. A controlling microprocessor may then clock out 18-bits of information and simultaneously strobe both parts. The cascaded ICs may be the same or different from the HIP0050. DR0 - DR7 Outputs 0 Thru 7 The drain output pins of the DMOS Power Drivers are capable of sinking 300mA. Each output has short circuit protection to independently shutdown the output under excessive high load current conditions. FLT Fault Flag The fault flag pin indicates an over-current in any one of the output drivers. (It is not an indicator for the thermal shutdown mode.) The FLT output is active low and can sink 1.6mA when activated. When latched low, it will remain latched until the next data strobe. EN Enable Pin The enable pin is an active low enable function for all eight output drivers. When EN is high, drive from the output data buffer is held low and all output drivers are disabled. When EN is low, the output drivers are enabled and data in the 8-bit shift register is transparent to the output data buffer. This input has a Schmitt trigger. LGND and GND Pins The LGND Pin is the 5V Logic Supply Ground for the IC and GND is a common ground for the power output drivers.
1000
100 ENERGY (mJ)
SAFE OPERATING AREA BELOW LINE 10
1
0.1
1 TIME (ms)
10
100
FIGURE 2. MAXIMUM SINGLE PULSE ENERGY SAFE OPERATING AREA FOR EACH CLAMPED OUTPUT DRIVER, TA = 25oC
5
HIP0050 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E20.3 (JEDEC MS-001-AD ISSUE D)
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.55 0.204 24.89 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 26.9 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.980 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 1.060 0.325 0.280
A
E A2 L A C L
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1
A1 A2
-C-
B B1 C D D1 E E1 e eA eB L N
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
0.100 BSC 0.300 BSC 0.115 20 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 20
2.93
6
HIP0050 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M24.3 (JEDEC MS-013-AD ISSUE C) 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A A1
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 15.20 7.40 MAX 2.65 0.30 0.51 0.32 15.60 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.5985 0.2914
MAX 0.1043 0.0118 0.020 0.0125 0.6141 0.2992
B C D E
A1 0.10(0.004) C
e H h L N
0.05 BSC 0.394 0.010 0.016 24 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 24 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
7

▲Up To Search▲

Price & Availability of HIP0050

	To Download HIP0050 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .